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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5563d 23h	/can/trunk/rtl/verilog/can_bsp.v
153	Arbitration capture register changed. SW reset (setting the reset_mode bit) doesn't work as HW reset.	igorm	7131d 23h	/can/trunk/rtl/verilog/can_bsp.v
152	Fixes for compatibility after the SW reset.	igorm	7136d 06h	/can/trunk/rtl/verilog/can_bsp.v
151	When CAN was reset by setting the reset_mode signal in mode register, it was possible that CAN was blocked for a short period of time. Problem occured very rarly.	igorm	7139d 00h	/can/trunk/rtl/verilog/can_bsp.v
149	Fixed synchronization problem in real hardware when 0xf is used for TSEG1.	igorm	7157d 23h	/can/trunk/rtl/verilog/can_bsp.v
145	Arbitration bug fixed.	igorm	7160d 12h	/can/trunk/rtl/verilog/can_bsp.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7326d 02h	/can/trunk/rtl/verilog/can_bsp.v
136	Error counters changed.	mohor	7420d 04h	/can/trunk/rtl/verilog/can_bsp.v
130	mbist signals updated according to newest convention	markom	7534d 12h	/can/trunk/rtl/verilog/can_bsp.v
129	Error counters changed.	mohor	7550d 21h	/can/trunk/rtl/verilog/can_bsp.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7551d 17h	/can/trunk/rtl/verilog/can_bsp.v
125	Synchronization changed, error counters fixed.	mohor	7555d 23h	/can/trunk/rtl/verilog/can_bsp.v
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7583d 11h	/can/trunk/rtl/verilog/can_bsp.v
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7625d 03h	/can/trunk/rtl/verilog/can_bsp.v
110	Fixed according to the linter.	mohor	7627d 03h	/can/trunk/rtl/verilog/can_bsp.v
107	Fixed according to the linter.	mohor	7627d 05h	/can/trunk/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7633d 16h	/can/trunk/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	7636d 07h	/can/trunk/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7640d 09h	/can/trunk/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7645d 21h	/can/trunk/rtl/verilog/can_bsp.v

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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