URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_defines.v] - Rev 163

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5602d 19h	/can/trunk/rtl/verilog/can_defines.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7364d 23h	/can/trunk/rtl/verilog/can_defines.v
137	Header changed.	mohor	7459d 00h	/can/trunk/rtl/verilog/can_defines.v
130	mbist signals updated according to newest convention	markom	7573d 09h	/can/trunk/rtl/verilog/can_defines.v
124	ALTERA_RAM supported.	mohor	7615d 02h	/can/trunk/rtl/verilog/can_defines.v
115	Artisan ram instances added.	simons	7636d 23h	/can/trunk/rtl/verilog/can_defines.v
95	Virtual silicon ram instances added.	simons	7684d 18h	/can/trunk/rtl/verilog/can_defines.v
71	Ports added for the CAN_BIST.	mohor	7703d 03h	/can/trunk/rtl/verilog/can_defines.v
64	* empty log message *	mohor	7783d 22h	/can/trunk/rtl/verilog/can_defines.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7792d 10h	/can/trunk/rtl/verilog/can_defines.v
51	Xilinx RAM added.	mohor	7799d 00h	/can/trunk/rtl/verilog/can_defines.v
48	Actel APA ram supported.	mohor	7802d 16h	/can/trunk/rtl/verilog/can_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7823d 12h	/can/trunk/rtl/verilog/can_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7867d 15h	/can/trunk/rtl/verilog/can_defines.v
2	Initial	mohor	7873d 22h	/can/trunk/rtl/verilog/can_defines.v