URL https://opencores.org/ocsvn/can/can/trunk

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[/] [can/] [trunk/] [rtl/] [verilog/] [can_register_syn.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5571d 20h	/can/trunk/rtl/verilog/can_register_syn.v
137	Header changed.	mohor	7428d 01h	/can/trunk/rtl/verilog/can_register_syn.v
58	timescale.v is used for simulation only.	mohor	7761d 23h	/can/trunk/rtl/verilog/can_register_syn.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7792d 13h	/can/trunk/rtl/verilog/can_register_syn.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7836d 16h	/can/trunk/rtl/verilog/can_register_syn.v
2	Initial	mohor	7842d 23h	/can/trunk/rtl/verilog/can_register_syn.v