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[/] [can/] [trunk/] [rtl] - Rev 118

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Rev Log message Author Age Path
118 Artisan RAM fixed (when not using BIST). mohor 7633d 11h /can/trunk/rtl
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7633d 11h /can/trunk/rtl
115 Artisan ram instances added. simons 7639d 05h /can/trunk/rtl
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7666d 06h /can/trunk/rtl
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7668d 06h /can/trunk/rtl
110 Fixed according to the linter. mohor 7668d 06h /can/trunk/rtl
109 Fixed according to the linter. mohor 7668d 07h /can/trunk/rtl
108 Fixed according to the linter. mohor 7668d 08h /can/trunk/rtl
107 Fixed according to the linter. mohor 7668d 08h /can/trunk/rtl
106 Unused signal removed. mohor 7674d 06h /can/trunk/rtl
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7674d 19h /can/trunk/rtl
102 Little fixes (to fix warnings). mohor 7677d 10h /can/trunk/rtl
100 Synchronization changed. mohor 7681d 12h /can/trunk/rtl
99 PCI_BIST replaced with CAN_BIST. mohor 7681d 12h /can/trunk/rtl
97 Overrun fifo implemented with FFs, because it is not possible to create such a memory. simons 7686d 23h /can/trunk/rtl
95 Virtual silicon ram instances added. simons 7687d 00h /can/trunk/rtl
93 synthesis full_case parallel_case fixed. mohor 7692d 12h /can/trunk/rtl
92 clkout is clk/2 after the reset. mohor 7692d 20h /can/trunk/rtl
90 paralel_case and full_case compiler directives added to case statements. mohor 7693d 09h /can/trunk/rtl
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7694d 06h /can/trunk/rtl

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