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[/] [can/] [trunk] - Rev 115

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Rev	Log message	Author	Age	Path
115	Artisan ram instances added.	simons	7732d 02h	/can/trunk
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7759d 03h	/can/trunk
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7761d 03h	/can/trunk
110	Fixed according to the linter.	mohor	7761d 03h	/can/trunk
109	Fixed according to the linter.	mohor	7761d 04h	/can/trunk
108	Fixed according to the linter.	mohor	7761d 05h	/can/trunk
107	Fixed according to the linter.	mohor	7761d 05h	/can/trunk
106	Unused signal removed.	mohor	7767d 03h	/can/trunk
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7767d 16h	/can/trunk
102	Little fixes (to fix warnings).	mohor	7770d 07h	/can/trunk
100	Synchronization changed.	mohor	7774d 09h	/can/trunk
99	PCI_BIST replaced with CAN_BIST.	mohor	7774d 09h	/can/trunk
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7779d 20h	/can/trunk
95	Virtual silicon ram instances added.	simons	7779d 21h	/can/trunk
93	synthesis full_case parallel_case fixed.	mohor	7785d 09h	/can/trunk
92	clkout is clk/2 after the reset.	mohor	7785d 17h	/can/trunk
90	paralel_case and full_case compiler directives added to case statements.	mohor	7786d 06h	/can/trunk
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7787d 03h	/can/trunk
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7787d 04h	/can/trunk
85	Typo fixed.	mohor	7788d 19h	/can/trunk

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