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[/] [common/] [tags/] [initial/] [generic_memories/] [rtl/] [verilog/] [generic_spram.v] - Rev 12

Rev	Log message	Author	Age	Path
12	Major cleanup. Files are now compliant to Altera & Xilinx memories. Memories are now compatible, i.e. drop-in replacements. Added synthesizeable generic FPGA description. Created "generic_memories" cvs entry.	rherveille	8365d 03h	/common/tags/initial/generic_memories/rtl/verilog/generic_spram.v