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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl] - Rev 65

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Rev Log message Author Age Path
65 DEV:
- design an Sram Wishbone memory with WAIT STATES.		 ameziti 4628d 19h /copyblaze/trunk/copyblaze/rtl/vhdl
63 DEV:
- design an Sram Wishbone memory.		 ameziti 4635d 20h /copyblaze/trunk/copyblaze/rtl/vhdl
59 PRJ:
- directory reorganisation		 ameziti 4636d 21h /copyblaze/trunk/copyblaze/rtl/vhdl
57 PRJ:
- new organisation of the rtl directory.		 ameziti 4636d 22h /copyblaze/trunk/copyblaze/rtl/vhdl
39 DEV:
- BUG : pop the stack also at "return I" instruction.		 ameziti 4648d 04h /copyblaze/trunk/copyblaze/rtl/vhdl
38 PRJ:
- remove automaticly generated code from svn.		 ameziti 4648d 04h /copyblaze/trunk/copyblaze/rtl/vhdl
32 SW:
- wishbone:
- add timer code software		 ameziti 4648d 18h /copyblaze/trunk/copyblaze/rtl/vhdl
28 SW
- add asm code for the "wb_gpio_08" wishbone validation test		 ameziti 4649d 07h /copyblaze/trunk/copyblaze/rtl/vhdl
22 DEV:
- wishbone :
- change the names of significants signals
- transport the data from the external component to phase2 write.		 ameziti 4652d 00h /copyblaze/trunk/copyblaze/rtl/vhdl
21 SIM:
- test the read wishbone instruction		 ameziti 4652d 01h /copyblaze/trunk/copyblaze/rtl/vhdl
19 DEV:
- wishbone address selection		 ameziti 4652d 01h /copyblaze/trunk/copyblaze/rtl/vhdl
18 DEV:
- correct some instructions selections		 ameziti 4652d 01h /copyblaze/trunk/copyblaze/rtl/vhdl
14 DOC:
- wishbone : add some comments		 ameziti 4652d 06h /copyblaze/trunk/copyblaze/rtl/vhdl
12 DEV:
- remove "Stall" management		 ameziti 4652d 06h /copyblaze/trunk/copyblaze/rtl/vhdl
9 SW:
- results of the execution on external ports		 ameziti 4652d 07h /copyblaze/trunk/copyblaze/rtl/vhdl
8 DEV
- developpement of the WbRdSing wishbone instruction		 ameziti 4652d 07h /copyblaze/trunk/copyblaze/rtl/vhdl
6 DEV:
- remove unused Wishbone signals		 ameziti 4652d 07h /copyblaze/trunk/copyblaze/rtl/vhdl
2 Import of the copyBlaze project. ameziti 4656d 01h /copyblaze/trunk/copyblaze/rtl/vhdl

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