URL https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk

Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [core.vhd] - Rev 5

Rev	Log message	Author	Age	Path
5	Bugfixes for all relationchips with interrupts BRK, IRQ and NMI. The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down. The "B" status flag was never set within BRK. The relationchip between addresses and data while writing onto the stack was badly misalligned.	fpga_is_funny	5890d 20h	/cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	fpga_is_funny	5899d 18h	/cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd
2	First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now.	fpga_is_funny	5899d 18h	/cpu6502_true_cycle/trunk/rtl/vhdl/core.vhd