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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [reg_sp.vhd] - Rev 14

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Rev	Log message	Author	Age	Path
14	More optimizations... - Second Phaze of removing unused nets & registers - Added Verilog source on demand by some customers (for trial use)	fpga_is_funny	5623d 17h	/cpu6502_true_cycle/trunk/rtl/vhdl/reg_sp.vhd
11	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead of $02FF and $0300)	fpga_is_funny	5628d 16h	/cpu6502_true_cycle/trunk/rtl/vhdl/reg_sp.vhd
5	Bugfixes for all relationchips with interrupts BRK, IRQ and NMI. The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down. The "B" status flag was never set within BRK. The relationchip between addresses and data while writing onto the stack was badly misalligned.	fpga_is_funny	5890d 20h	/cpu6502_true_cycle/trunk/rtl/vhdl/reg_sp.vhd
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	fpga_is_funny	5899d 18h	/cpu6502_true_cycle/trunk/rtl/vhdl/reg_sp.vhd
2	First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now.	fpga_is_funny	5899d 18h	/cpu6502_true_cycle/trunk/rtl/vhdl/reg_sp.vhd

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