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[/] [cpu65c02_true_cycle/] [trunk] - Rev 24

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24 v1.53 PRODUCTION - containing bug fixes related to v1.52 ("BASIC" pre-variant)
v2.00 PRODUCTION - related to RELEASE CANDIDATE ("HIGH SPEED" pre-variant)		 fpga_is_funny 1198d 05h /cpu65c02_true_cycle/trunk
23 Added "beta" section to separate upcoming beta versions or release candidates from released versions.
The currently released version moved to "released".
The upcoming v2.00rc loaded into "beta" is a major release candidate containing performance improvements.
fmax is now typical from 110 MHz to 180 MHz even for low/middle cost FPGA devices. High end FPGA devices allow clock rates over 250 MHz now.
After many cycle count issues caused by description errors in original vendor documents, the v2.00rc testing processes (in progress) rely on the WDC 65C02 documentation and physical chips for reference now.		 fpga_is_funny 2057d 06h /cpu65c02_true_cycle/trunk
22 v1.52 PRODUCTION
RESET generates SYNC now, 1 dead cycle delayed		 fpga_is_funny 2091d 10h /cpu65c02_true_cycle/trunk
21 fpga_is_funny 2092d 08h /cpu65c02_true_cycle/trunk
20 fpga_is_funny 2092d 08h /cpu65c02_true_cycle/trunk
19 fpga_is_funny 3956d 12h /cpu65c02_true_cycle/trunk
18 RELEASE CANDIDATE V1.5 RC of r65c02_tc.
Major Bug Fixes are available.
Look at the header of r65c02_tc.vhd to get more details.
Because of translation errors made by a third party conversion tool in the past, Verilog sources are no longer available. May be re-activated in the future.

The upcoming PRODUCTION version will be include some enhancements for speed and resource utilization.		 fpga_is_funny 3956d 13h /cpu65c02_true_cycle/trunk
15 New directory structure. root 5563d 01h /cpu65c02_true_cycle/trunk
14 Obsolete file fpga_is_funny 5566d 22h /trunk
13 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)		 fpga_is_funny 5575d 02h /trunk
12 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)		 fpga_is_funny 5575d 02h /trunk
11 no message fpga_is_funny 5626d 21h /trunk
10 no message fpga_is_funny 5626d 21h /trunk
9 no message fpga_is_funny 5626d 22h /trunk
8 no message fpga_is_funny 5626d 22h /trunk
7 - Delete unused nets and blocks (same as R6502_TC)
- Rename blocks
- Re-arrage FSM symbols in block FSM_Execution_Unit		 fpga_is_funny 5626d 22h /trunk
5 This commit was generated by cvs2svn to compensate for changes in r4, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5661d 03h /trunk
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5779d 01h /trunk
1 Standard project directories initialized by cvs2svn. 5779d 01h /trunk

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