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[/] [dbg_interface/] [tags/] [asyst_3/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5637d 13h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
154	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		7434d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
144	Port names and defines for the supported CPUs changed.	igorm	7441d 21h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
139	New release of the debug interface (3rd. release).	igorm	7445d 13h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
138	Temp version before changing dbg interface.	igorm	7451d 17h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7503d 23h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
123	All flipflops are reset.	mohor	7508d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
117	Define name changed.	mohor	7513d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7515d 02h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
106	Sensitivity list updated.	simons	7516d 00h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
101	Almost finished.	mohor	7516d 16h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
99	cpu registers added.	mohor	7517d 18h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
95	Temp version.	mohor	7519d 10h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7541d 18h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
73	CRC logic changed.	mohor	7602d 17h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
67	Lower two address lines must be always zero.	simons	7637d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
65	WB_CNTL register added, some syncronization fixes.	simons	7638d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
63	Three more chains added for cpu debug access.	simons	7658d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
57	Multiple cpu support added.	simons	7686d 21h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7953d 19h	/dbg_interface/tags/asyst_3/rtl/verilog/dbg_top.v

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[/] [dbg_interface/] [tags/] [asyst_3/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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