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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] [verilog/] [dbg_tb.v] - Rev 110

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Rev Log message Author Age Path
110 Waiting for "ready" improved. mohor 7514d 22h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
102 New version. mohor 7516d 17h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
101 Almost finished. mohor 7516d 18h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
99 cpu registers added. mohor 7517d 20h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
96 Working. mohor 7519d 00h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
95 Temp version. mohor 7519d 12h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
93 tmp version. mohor 7520d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
92 temp version. mohor 7524d 03h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
91 tmp version. mohor 7524d 22h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
90 tmp version. mohor 7525d 17h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
89 temp4 version. mohor 7526d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
88 temp3 version. mohor 7527d 18h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
87 tmp2 version. mohor 7528d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
80 New version of the debug interface. Not finished, yet. mohor 7541d 20h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
73 CRC logic changed. mohor 7602d 19h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
63 Three more chains added for cpu debug access. simons 7658d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8136d 20h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
38 Few outputs for boundary scan chain added. mohor 8192d 20h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
36 Structure changed. Hooks for jtag chain added. mohor 8196d 19h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8336d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v

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