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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] [verilog/] [dbg_tb.v] - Rev 128

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Rev Log message Author Age Path
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7567d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
124 Display for VATS added. mohor 7572d 18h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
121 Port signals are all set to zero after reset. mohor 7575d 18h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
120 test stall_test added. mohor 7575d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
117 Define name changed. mohor 7577d 17h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
116 Data latching changed when testing WB. mohor 7577d 18h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
115 More debug data added. mohor 7577d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
114 CRC generation iand verification in bench changed. mohor 7577d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
113 IDCODE test improved. mohor 7578d 00h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
111 Define tap_defines.v added to test bench. mohor 7578d 19h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
110 Waiting for "ready" improved. mohor 7578d 19h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
102 New version. mohor 7580d 14h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
101 Almost finished. mohor 7580d 15h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
99 cpu registers added. mohor 7581d 17h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
96 Working. mohor 7582d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
95 Temp version. mohor 7583d 09h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
93 tmp version. mohor 7584d 20h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
92 temp version. mohor 7588d 00h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
91 tmp version. mohor 7588d 19h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
90 tmp version. mohor 7589d 14h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v

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