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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] [verilog/] [dbg_tb.v] - Rev 93

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Rev Log message Author Age Path
93 tmp version. mohor 7521d 00h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
92 temp version. mohor 7524d 04h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
91 tmp version. mohor 7524d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
90 tmp version. mohor 7525d 17h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
89 temp4 version. mohor 7526d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
88 temp3 version. mohor 7527d 18h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
87 tmp2 version. mohor 7528d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
80 New version of the debug interface. Not finished, yet. mohor 7541d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
73 CRC logic changed. mohor 7602d 19h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
63 Three more chains added for cpu debug access. simons 7658d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8136d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
38 Few outputs for boundary scan chain added. mohor 8192d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
36 Structure changed. Hooks for jtag chain added. mohor 8196d 20h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8337d 00h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
15 bs_chain_o added. mohor 8339d 01h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
13 Signal names changed to lowercase. mohor 8340d 01h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8341d 01h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8361d 21h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
9 Working version. Few bugs fixed, comments added. mohor 8366d 01h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
6 Minor changes for simulation. mohor 8366d 23h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v

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