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[/] [dbg_interface/] [tags/] [highland_ver1/] [rtl/] [verilog/] [dbg_defines.v] - Rev 158

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158 root 5590d 21h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
133 This commit was manufactured by cvs2svn to create tag 'highland_ver1'. 7412d 23h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7457d 07h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
117 Define name changed. mohor 7467d 03h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7495d 02h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
73 CRC logic changed. mohor 7556d 01h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
71 Mbist support added. simons 7558d 07h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
65 WB_CNTL register added, some syncronization fixes. simons 7592d 02h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
63 Three more chains added for cpu debug access. simons 7612d 03h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
57 Multiple cpu support added. simons 7640d 05h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8090d 02h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8192d 09h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
27 Warnings from synthesys tools fixed. mohor 8242d 07h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
23 Trace disabled by default. mohor 8250d 07h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8294d 07h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8315d 03h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
9 Working version. Few bugs fixed, comments added. mohor 8319d 07h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
5 Trace fixed. Some registers changed, trace simplified. mohor 8321d 03h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v
2 Initial official release. mohor 8326d 03h /dbg_interface/tags/highland_ver1/rtl/verilog/dbg_defines.v

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