OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog/] [dbg_defines.v] - Rev 158

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5602d 05h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
78 This commit was manufactured by cvs2svn to create tag 'old_debug'. 7567d 07h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
73 CRC logic changed. mohor 7567d 09h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
71 Mbist support added. simons 7569d 15h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
65 WB_CNTL register added, some syncronization fixes. simons 7603d 10h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
63 Three more chains added for cpu debug access. simons 7623d 11h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
57 Multiple cpu support added. simons 7651d 13h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8101d 10h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8203d 17h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
27 Warnings from synthesys tools fixed. mohor 8253d 15h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
23 Trace disabled by default. mohor 8261d 15h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8305d 15h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8326d 11h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
9 Working version. Few bugs fixed, comments added. mohor 8330d 15h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
5 Trace fixed. Some registers changed, trace simplified. mohor 8332d 11h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v
2 Initial official release. mohor 8337d 11h /dbg_interface/tags/old_debug/rtl/verilog/dbg_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.