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[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5609d 03h	/dbg_interface/tags/old_debug/rtl/verilog
78	This commit was manufactured by cvs2svn to create tag 'old_debug'.		7574d 05h	/dbg_interface/tags/old_debug/rtl/verilog
77	MBIST chain connection fixed.	mohor	7574d 05h	/dbg_interface/tags/old_debug/rtl/verilog
73	CRC logic changed.	mohor	7574d 07h	/dbg_interface/tags/old_debug/rtl/verilog
71	Mbist support added.	simons	7576d 13h	/dbg_interface/tags/old_debug/rtl/verilog
67	Lower two address lines must be always zero.	simons	7609d 09h	/dbg_interface/tags/old_debug/rtl/verilog
65	WB_CNTL register added, some syncronization fixes.	simons	7610d 09h	/dbg_interface/tags/old_debug/rtl/verilog
63	Three more chains added for cpu debug access.	simons	7630d 09h	/dbg_interface/tags/old_debug/rtl/verilog
61	Lapsus fixed.	simons	7658d 09h	/dbg_interface/tags/old_debug/rtl/verilog
59	Reset value for riscsel register set to 1.	simons	7658d 10h	/dbg_interface/tags/old_debug/rtl/verilog
57	Multiple cpu support added.	simons	7658d 11h	/dbg_interface/tags/old_debug/rtl/verilog
53	Trst active high. Inverted on higher layer.	mohor	7925d 09h	/dbg_interface/tags/old_debug/rtl/verilog
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7925d 09h	/dbg_interface/tags/old_debug/rtl/verilog
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7952d 21h	/dbg_interface/tags/old_debug/rtl/verilog
47	mon_cntl_o signals that controls monitor mux added.	mohor	8108d 08h	/dbg_interface/tags/old_debug/rtl/verilog
46	Asynchronous reset used instead of synchronous.	mohor	8116d 15h	/dbg_interface/tags/old_debug/rtl/verilog
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8123d 10h	/dbg_interface/tags/old_debug/rtl/verilog
44	Signal names changed to lower case.	mohor	8123d 10h	/dbg_interface/tags/old_debug/rtl/verilog
43	Intentional error removed.	mohor	8128d 10h	/dbg_interface/tags/old_debug/rtl/verilog
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8128d 12h	/dbg_interface/tags/old_debug/rtl/verilog

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog] - Rev 158

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