URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog] - Rev 17

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8290d 13h	/dbg_interface/tags/old_debug/rtl/verilog
15	bs_chain_o added.	mohor	8292d 14h	/dbg_interface/tags/old_debug/rtl/verilog
13	Signal names changed to lowercase.	mohor	8293d 15h	/dbg_interface/tags/old_debug/rtl/verilog
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8294d 15h	/dbg_interface/tags/old_debug/rtl/verilog
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8315d 11h	/dbg_interface/tags/old_debug/rtl/verilog
9	Working version. Few bugs fixed, comments added.	mohor	8319d 14h	/dbg_interface/tags/old_debug/rtl/verilog
8	Asynchronous set/reset not used in trace any more.	mohor	8320d 13h	/dbg_interface/tags/old_debug/rtl/verilog
5	Trace fixed. Some registers changed, trace simplified.	mohor	8321d 10h	/dbg_interface/tags/old_debug/rtl/verilog
2	Initial official release.	mohor	8326d 11h	/dbg_interface/tags/old_debug/rtl/verilog