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[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog] - Rev 39

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Rev	Log message	Author	Age	Path
39	tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just not named correctly.	mohor	8151d 07h	/dbg_interface/tags/old_debug/rtl/verilog
38	Few outputs for boundary scan chain added.	mohor	8164d 05h	/dbg_interface/tags/old_debug/rtl/verilog
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8164d 09h	/dbg_interface/tags/old_debug/rtl/verilog
36	Structure changed. Hooks for jtag chain added.	mohor	8168d 05h	/dbg_interface/tags/old_debug/rtl/verilog
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8198d 08h	/dbg_interface/tags/old_debug/rtl/verilog
32	Stupid bug that was entered by previous update fixed.	mohor	8199d 06h	/dbg_interface/tags/old_debug/rtl/verilog
31	trst synchronization is not needed and was removed.	mohor	8199d 07h	/dbg_interface/tags/old_debug/rtl/verilog
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8210d 12h	/dbg_interface/tags/old_debug/rtl/verilog
28	TDO and TDO Enable signal are separated into two signals.	mohor	8246d 09h	/dbg_interface/tags/old_debug/rtl/verilog
27	Warnings from synthesys tools fixed.	mohor	8260d 10h	/dbg_interface/tags/old_debug/rtl/verilog
26	Warnings from synthesys tools fixed.	mohor	8260d 10h	/dbg_interface/tags/old_debug/rtl/verilog
25	trst signal is synchronized to wb_clk_i.	mohor	8261d 07h	/dbg_interface/tags/old_debug/rtl/verilog
23	Trace disabled by default.	mohor	8268d 10h	/dbg_interface/tags/old_debug/rtl/verilog
22	Register length fixed.	mohor	8268d 10h	/dbg_interface/tags/old_debug/rtl/verilog
21	CRC is returned when chain selection data is transmitted.	mohor	8269d 06h	/dbg_interface/tags/old_debug/rtl/verilog
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8270d 09h	/dbg_interface/tags/old_debug/rtl/verilog
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8282d 10h	/dbg_interface/tags/old_debug/rtl/verilog
18	Reset signals are not combined any more.	mohor	8284d 19h	/dbg_interface/tags/old_debug/rtl/verilog
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8308d 08h	/dbg_interface/tags/old_debug/rtl/verilog
15	bs_chain_o added.	mohor	8310d 09h	/dbg_interface/tags/old_debug/rtl/verilog

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[/] [dbg_interface/] [tags/] [old_debug/] [rtl/] [verilog] - Rev 39

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