OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [dbg_top.v] - Rev 21

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
21 CRC is returned when chain selection data is transmitted. mohor 8262d 08h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8263d 11h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8275d 11h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
18 Reset signals are not combined any more. mohor 8277d 20h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8301d 10h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
15 bs_chain_o added. mohor 8303d 11h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
13 Signal names changed to lowercase. mohor 8304d 11h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8305d 11h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8326d 07h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
9 Working version. Few bugs fixed, comments added. mohor 8330d 11h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
8 Asynchronous set/reset not used in trace any more. mohor 8331d 09h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
5 Trace fixed. Some registers changed, trace simplified. mohor 8332d 07h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v
2 Initial official release. mohor 8337d 08h /dbg_interface/tags/rel_1/rtl/verilog/dbg_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.