URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_1/] [rtl/] [verilog/] [dbg_trace.v] - Rev 158

Rev	Log message	Author	Age	Path
158		root	5615d 00h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
48	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8114d 05h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8276d 09h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8314d 09h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
9	Working version. Few bugs fixed, comments added.	mohor	8343d 10h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
8	Asynchronous set/reset not used in trace any more.	mohor	8344d 08h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8345d 06h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v
2	Initial official release.	mohor	8350d 06h	/dbg_interface/tags/rel_1/rtl/verilog/dbg_trace.v