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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 93

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Rev Log message Author Age Path
93 tmp version. mohor 7510d 23h /dbg_interface/tags/rel_15/rtl
92 temp version. mohor 7514d 03h /dbg_interface/tags/rel_15/rtl
91 tmp version. mohor 7514d 22h /dbg_interface/tags/rel_15/rtl
90 tmp version. mohor 7515d 17h /dbg_interface/tags/rel_15/rtl
89 temp4 version. mohor 7516d 23h /dbg_interface/tags/rel_15/rtl
88 temp3 version. mohor 7517d 17h /dbg_interface/tags/rel_15/rtl
87 tmp2 version. mohor 7518d 22h /dbg_interface/tags/rel_15/rtl
86 Tmp version. mohor 7531d 18h /dbg_interface/tags/rel_15/rtl
83 Small fix. mohor 7531d 19h /dbg_interface/tags/rel_15/rtl
82 New directory structure. New version of the debug interface. mohor 7531d 20h /dbg_interface/tags/rel_15/rtl
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7531d 20h /dbg_interface/tags/rel_15/rtl
77 MBIST chain connection fixed. mohor 7592d 17h /dbg_interface/tags/rel_15/rtl
73 CRC logic changed. mohor 7592d 18h /dbg_interface/tags/rel_15/rtl
71 Mbist support added. simons 7595d 01h /dbg_interface/tags/rel_15/rtl
67 Lower two address lines must be always zero. simons 7627d 21h /dbg_interface/tags/rel_15/rtl
65 WB_CNTL register added, some syncronization fixes. simons 7628d 20h /dbg_interface/tags/rel_15/rtl
63 Three more chains added for cpu debug access. simons 7648d 21h /dbg_interface/tags/rel_15/rtl
61 Lapsus fixed. simons 7676d 21h /dbg_interface/tags/rel_15/rtl
59 Reset value for riscsel register set to 1. simons 7676d 21h /dbg_interface/tags/rel_15/rtl
57 Multiple cpu support added. simons 7676d 22h /dbg_interface/tags/rel_15/rtl

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