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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_defines.v] - Rev 81

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Rev Log message Author Age Path
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7511d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
73 CRC logic changed. mohor 7572d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
71 Mbist support added. simons 7574d 20h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
65 WB_CNTL register added, some syncronization fixes. simons 7608d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
63 Three more chains added for cpu debug access. simons 7628d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
57 Multiple cpu support added. simons 7656d 17h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8106d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8208d 21h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
27 Warnings from synthesys tools fixed. mohor 8258d 19h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
23 Trace disabled by default. mohor 8266d 20h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8310d 19h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8331d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
9 Working version. Few bugs fixed, comments added. mohor 8335d 19h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
5 Trace fixed. Some registers changed, trace simplified. mohor 8337d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v
2 Initial official release. mohor 8342d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_defines.v

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