OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 101

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
101 Almost finished. mohor 7486d 11h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
99 cpu registers added. mohor 7487d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
95 Temp version. mohor 7489d 05h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7511d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
73 CRC logic changed. mohor 7572d 11h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
67 Lower two address lines must be always zero. simons 7607d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
65 WB_CNTL register added, some syncronization fixes. simons 7608d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
63 Three more chains added for cpu debug access. simons 7628d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
57 Multiple cpu support added. simons 7656d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7923d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7951d 01h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8106d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
44 Signal names changed to lower case. mohor 8121d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
43 Intentional error removed. mohor 8126d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
42 A block for checking possible simulation/synthesis missmatch added. mohor 8126d 17h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8162d 17h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
36 Structure changed. Hooks for jtag chain added. mohor 8166d 12h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8196d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
32 Stupid bug that was entered by previous update fixed. mohor 8197d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
31 trst synchronization is not needed and was removed. mohor 8197d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.