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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 51

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Rev	Log message	Author	Age	Path
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7980d 21h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8136d 09h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8151d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
43	Intentional error removed.	mohor	8156d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8156d 13h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8192d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8196d 09h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8226d 12h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8227d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8227d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8238d 16h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
28	TDO and TDO Enable signal are separated into two signals.	mohor	8274d 13h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
25	trst signal is synchronized to wb_clk_i.	mohor	8289d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
22	Register length fixed.	mohor	8296d 15h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
21	CRC is returned when chain selection data is transmitted.	mohor	8297d 11h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8298d 13h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8310d 14h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
18	Reset signals are not combined any more.	mohor	8312d 23h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8336d 12h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
15	bs_chain_o added.	mohor	8338d 13h	/dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 51

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