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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog] - Rev 91

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Rev Log message Author Age Path
91 tmp version. mohor 7495d 05h /dbg_interface/tags/rel_15/rtl/verilog
90 tmp version. mohor 7495d 23h /dbg_interface/tags/rel_15/rtl/verilog
89 temp4 version. mohor 7497d 05h /dbg_interface/tags/rel_15/rtl/verilog
88 temp3 version. mohor 7498d 00h /dbg_interface/tags/rel_15/rtl/verilog
87 tmp2 version. mohor 7499d 05h /dbg_interface/tags/rel_15/rtl/verilog
86 Tmp version. mohor 7512d 01h /dbg_interface/tags/rel_15/rtl/verilog
83 Small fix. mohor 7512d 02h /dbg_interface/tags/rel_15/rtl/verilog
82 New directory structure. New version of the debug interface. mohor 7512d 02h /dbg_interface/tags/rel_15/rtl/verilog
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7512d 02h /dbg_interface/tags/rel_15/rtl/verilog
77 MBIST chain connection fixed. mohor 7572d 23h /dbg_interface/tags/rel_15/rtl/verilog
73 CRC logic changed. mohor 7573d 01h /dbg_interface/tags/rel_15/rtl/verilog
71 Mbist support added. simons 7575d 08h /dbg_interface/tags/rel_15/rtl/verilog
67 Lower two address lines must be always zero. simons 7608d 03h /dbg_interface/tags/rel_15/rtl/verilog
65 WB_CNTL register added, some syncronization fixes. simons 7609d 03h /dbg_interface/tags/rel_15/rtl/verilog
63 Three more chains added for cpu debug access. simons 7629d 03h /dbg_interface/tags/rel_15/rtl/verilog
61 Lapsus fixed. simons 7657d 03h /dbg_interface/tags/rel_15/rtl/verilog
59 Reset value for riscsel register set to 1. simons 7657d 04h /dbg_interface/tags/rel_15/rtl/verilog
57 Multiple cpu support added. simons 7657d 05h /dbg_interface/tags/rel_15/rtl/verilog
53 Trst active high. Inverted on higher layer. mohor 7924d 03h /dbg_interface/tags/rel_15/rtl/verilog
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7924d 03h /dbg_interface/tags/rel_15/rtl/verilog

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