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[/] [dbg_interface/] [tags/] [rel_19/] [bench/] [verilog] - Rev 87

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Rev Log message Author Age Path
87 tmp2 version. mohor 7494d 12h /dbg_interface/tags/rel_19/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7507d 09h /dbg_interface/tags/rel_19/bench/verilog
75 Simulation files. mohor 7568d 07h /dbg_interface/tags/rel_19/bench/verilog
73 CRC logic changed. mohor 7568d 08h /dbg_interface/tags/rel_19/bench/verilog
63 Three more chains added for cpu debug access. simons 7624d 10h /dbg_interface/tags/rel_19/bench/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8102d 09h /dbg_interface/tags/rel_19/bench/verilog
38 Few outputs for boundary scan chain added. mohor 8158d 09h /dbg_interface/tags/rel_19/bench/verilog
36 Structure changed. Hooks for jtag chain added. mohor 8162d 08h /dbg_interface/tags/rel_19/bench/verilog
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8302d 12h /dbg_interface/tags/rel_19/bench/verilog
15 bs_chain_o added. mohor 8304d 13h /dbg_interface/tags/rel_19/bench/verilog
13 Signal names changed to lowercase. mohor 8305d 14h /dbg_interface/tags/rel_19/bench/verilog
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8306d 14h /dbg_interface/tags/rel_19/bench/verilog
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8327d 10h /dbg_interface/tags/rel_19/bench/verilog
9 Working version. Few bugs fixed, comments added. mohor 8331d 14h /dbg_interface/tags/rel_19/bench/verilog
6 Minor changes for simulation. mohor 8332d 12h /dbg_interface/tags/rel_19/bench/verilog
5 Trace fixed. Some registers changed, trace simplified. mohor 8333d 10h /dbg_interface/tags/rel_19/bench/verilog
2 Initial official release. mohor 8338d 10h /dbg_interface/tags/rel_19/bench/verilog

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