OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] [verilog] - Rev 89

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
89 temp4 version. mohor 7520d 19h /dbg_interface/tags/rel_19/bench/verilog
88 temp3 version. mohor 7521d 14h /dbg_interface/tags/rel_19/bench/verilog
87 tmp2 version. mohor 7522d 19h /dbg_interface/tags/rel_19/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7535d 17h /dbg_interface/tags/rel_19/bench/verilog
75 Simulation files. mohor 7596d 15h /dbg_interface/tags/rel_19/bench/verilog
73 CRC logic changed. mohor 7596d 15h /dbg_interface/tags/rel_19/bench/verilog
63 Three more chains added for cpu debug access. simons 7652d 17h /dbg_interface/tags/rel_19/bench/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8130d 16h /dbg_interface/tags/rel_19/bench/verilog
38 Few outputs for boundary scan chain added. mohor 8186d 16h /dbg_interface/tags/rel_19/bench/verilog
36 Structure changed. Hooks for jtag chain added. mohor 8190d 16h /dbg_interface/tags/rel_19/bench/verilog
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8330d 19h /dbg_interface/tags/rel_19/bench/verilog
15 bs_chain_o added. mohor 8332d 20h /dbg_interface/tags/rel_19/bench/verilog
13 Signal names changed to lowercase. mohor 8333d 21h /dbg_interface/tags/rel_19/bench/verilog
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8334d 21h /dbg_interface/tags/rel_19/bench/verilog
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8355d 17h /dbg_interface/tags/rel_19/bench/verilog
9 Working version. Few bugs fixed, comments added. mohor 8359d 21h /dbg_interface/tags/rel_19/bench/verilog
6 Minor changes for simulation. mohor 8360d 19h /dbg_interface/tags/rel_19/bench/verilog
5 Trace fixed. Some registers changed, trace simplified. mohor 8361d 17h /dbg_interface/tags/rel_19/bench/verilog
2 Initial official release. mohor 8366d 17h /dbg_interface/tags/rel_19/bench/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.