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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench] - Rev 92

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Rev	Log message	Author	Age	Path
92	temp version.	mohor	7482d 08h	/dbg_interface/tags/rel_19/bench
91	tmp version.	mohor	7483d 03h	/dbg_interface/tags/rel_19/bench
90	tmp version.	mohor	7483d 22h	/dbg_interface/tags/rel_19/bench
89	temp4 version.	mohor	7485d 04h	/dbg_interface/tags/rel_19/bench
88	temp3 version.	mohor	7485d 23h	/dbg_interface/tags/rel_19/bench
87	tmp2 version.	mohor	7487d 04h	/dbg_interface/tags/rel_19/bench
80	New version of the debug interface. Not finished, yet.	mohor	7500d 01h	/dbg_interface/tags/rel_19/bench
75	Simulation files.	mohor	7560d 23h	/dbg_interface/tags/rel_19/bench
73	CRC logic changed.	mohor	7561d 00h	/dbg_interface/tags/rel_19/bench
63	Three more chains added for cpu debug access.	simons	7617d 02h	/dbg_interface/tags/rel_19/bench
47	mon_cntl_o signals that controls monitor mux added.	mohor	8095d 01h	/dbg_interface/tags/rel_19/bench
38	Few outputs for boundary scan chain added.	mohor	8151d 01h	/dbg_interface/tags/rel_19/bench
36	Structure changed. Hooks for jtag chain added.	mohor	8155d 00h	/dbg_interface/tags/rel_19/bench
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8295d 04h	/dbg_interface/tags/rel_19/bench
15	bs_chain_o added.	mohor	8297d 05h	/dbg_interface/tags/rel_19/bench
13	Signal names changed to lowercase.	mohor	8298d 06h	/dbg_interface/tags/rel_19/bench
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8299d 06h	/dbg_interface/tags/rel_19/bench
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8320d 02h	/dbg_interface/tags/rel_19/bench
9	Working version. Few bugs fixed, comments added.	mohor	8324d 06h	/dbg_interface/tags/rel_19/bench
6	Minor changes for simulation.	mohor	8325d 04h	/dbg_interface/tags/rel_19/bench

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench] - Rev 92

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