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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] [dbg_wb.v] - Rev 158

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Rev Log message Author Age Path
158 root 5635d 23h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
127 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7505d 08h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
123 All flipflops are reset. mohor 7507d 05h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
121 Port signals are all set to zero after reset. mohor 7510d 05h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7513d 11h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
102 New version. mohor 7515d 01h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
99 cpu registers added. mohor 7516d 04h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
97 Working. mohor 7517d 07h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
95 Temp version. mohor 7517d 20h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
94 temp version. Resets will be changed in next version. mohor 7518d 07h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
93 tmp version. mohor 7519d 08h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
92 temp version. mohor 7522d 11h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
91 tmp version. mohor 7523d 06h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
90 tmp version. mohor 7524d 01h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
89 temp4 version. mohor 7525d 07h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
88 temp3 version. mohor 7526d 02h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
87 tmp2 version. mohor 7527d 07h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
86 Tmp version. mohor 7540d 03h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
83 Small fix. mohor 7540d 04h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v
82 New directory structure. New version of the debug interface. mohor 7540d 04h /dbg_interface/tags/rel_19/rtl/verilog/dbg_wb.v

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