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[/] [dbg_interface/] [tags/] [rel_19] - Rev 19

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Rev Log message Author Age Path
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8277d 12h /dbg_interface/tags/rel_19
18 Reset signals are not combined any more. mohor 8279d 21h /dbg_interface/tags/rel_19
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8303d 11h /dbg_interface/tags/rel_19
16 bs_chain_o port added. mohor 8305d 11h /dbg_interface/tags/rel_19
15 bs_chain_o added. mohor 8305d 12h /dbg_interface/tags/rel_19
14 Document updated. mohor 8306d 09h /dbg_interface/tags/rel_19
13 Signal names changed to lowercase. mohor 8306d 12h /dbg_interface/tags/rel_19
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8307d 13h /dbg_interface/tags/rel_19
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8328d 08h /dbg_interface/tags/rel_19
10 First official release 1.0. mohor 8332d 12h /dbg_interface/tags/rel_19
9 Working version. Few bugs fixed, comments added. mohor 8332d 12h /dbg_interface/tags/rel_19
8 Asynchronous set/reset not used in trace any more. mohor 8333d 11h /dbg_interface/tags/rel_19
7 First official release 1.0. mohor 8333d 11h /dbg_interface/tags/rel_19
6 Minor changes for simulation. mohor 8333d 11h /dbg_interface/tags/rel_19
5 Trace fixed. Some registers changed, trace simplified. mohor 8334d 08h /dbg_interface/tags/rel_19
4 Initial official release. mohor 8339d 08h /dbg_interface/tags/rel_19
2 Initial official release. mohor 8339d 09h /dbg_interface/tags/rel_19
1 Standard project directories initialized by cvs2svn. 8339d 09h /dbg_interface/tags/rel_19

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