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[/] [dbg_interface/] [tags/] [rel_19] - Rev 69

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69 WBCNTL added, multiple CPU support described. simons 7600d 04h /dbg_interface/tags/rel_19
67 Lower two address lines must be always zero. simons 7605d 09h /dbg_interface/tags/rel_19
65 WB_CNTL register added, some syncronization fixes. simons 7606d 08h /dbg_interface/tags/rel_19
63 Three more chains added for cpu debug access. simons 7626d 09h /dbg_interface/tags/rel_19
61 Lapsus fixed. simons 7654d 09h /dbg_interface/tags/rel_19
59 Reset value for riscsel register set to 1. simons 7654d 09h /dbg_interface/tags/rel_19
57 Multiple cpu support added. simons 7654d 10h /dbg_interface/tags/rel_19
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7921d 07h /dbg_interface/tags/rel_19
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7921d 07h /dbg_interface/tags/rel_19
53 Trst active high. Inverted on higher layer. mohor 7921d 08h /dbg_interface/tags/rel_19
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7921d 08h /dbg_interface/tags/rel_19
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7948d 20h /dbg_interface/tags/rel_19
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7948d 21h /dbg_interface/tags/rel_19
47 mon_cntl_o signals that controls monitor mux added. mohor 8104d 08h /dbg_interface/tags/rel_19
46 Asynchronous reset used instead of synchronous. mohor 8112d 14h /dbg_interface/tags/rel_19
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8119d 10h /dbg_interface/tags/rel_19
44 Signal names changed to lower case. mohor 8119d 10h /dbg_interface/tags/rel_19
43 Intentional error removed. mohor 8124d 09h /dbg_interface/tags/rel_19
42 A block for checking possible simulation/synthesis missmatch added. mohor 8124d 11h /dbg_interface/tags/rel_19
41 Function changed to logic because of some synthesis warnings. mohor 8132d 08h /dbg_interface/tags/rel_19

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