OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] - Rev 67

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
67 Lower two address lines must be always zero. simons 7639d 09h /dbg_interface/tags/rel_21
65 WB_CNTL register added, some syncronization fixes. simons 7640d 08h /dbg_interface/tags/rel_21
63 Three more chains added for cpu debug access. simons 7660d 09h /dbg_interface/tags/rel_21
61 Lapsus fixed. simons 7688d 09h /dbg_interface/tags/rel_21
59 Reset value for riscsel register set to 1. simons 7688d 09h /dbg_interface/tags/rel_21
57 Multiple cpu support added. simons 7688d 10h /dbg_interface/tags/rel_21
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 7955d 07h /dbg_interface/tags/rel_21
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 7955d 07h /dbg_interface/tags/rel_21
53 Trst active high. Inverted on higher layer. mohor 7955d 08h /dbg_interface/tags/rel_21
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7955d 08h /dbg_interface/tags/rel_21
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7982d 20h /dbg_interface/tags/rel_21
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7982d 21h /dbg_interface/tags/rel_21
47 mon_cntl_o signals that controls monitor mux added. mohor 8138d 08h /dbg_interface/tags/rel_21
46 Asynchronous reset used instead of synchronous. mohor 8146d 14h /dbg_interface/tags/rel_21
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8153d 10h /dbg_interface/tags/rel_21
44 Signal names changed to lower case. mohor 8153d 10h /dbg_interface/tags/rel_21
43 Intentional error removed. mohor 8158d 09h /dbg_interface/tags/rel_21
42 A block for checking possible simulation/synthesis missmatch added. mohor 8158d 11h /dbg_interface/tags/rel_21
41 Function changed to logic because of some synthesis warnings. mohor 8166d 08h /dbg_interface/tags/rel_21
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8180d 08h /dbg_interface/tags/rel_21

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.