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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5587d 03h	/dbg_interface/tags/rel_21/bench
134	This commit was manufactured by cvs2svn to create tag 'rel_21'.		7409d 06h	/dbg_interface/tags/rel_21/bench
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7453d 13h	/dbg_interface/tags/rel_21/bench
124	Display for VATS added.	mohor	7458d 09h	/dbg_interface/tags/rel_21/bench
121	Port signals are all set to zero after reset.	mohor	7461d 09h	/dbg_interface/tags/rel_21/bench
120	test stall_test added.	mohor	7461d 12h	/dbg_interface/tags/rel_21/bench
117	Define name changed.	mohor	7463d 09h	/dbg_interface/tags/rel_21/bench
116	Data latching changed when testing WB.	mohor	7463d 09h	/dbg_interface/tags/rel_21/bench
115	More debug data added.	mohor	7463d 13h	/dbg_interface/tags/rel_21/bench
114	CRC generation iand verification in bench changed.	mohor	7463d 14h	/dbg_interface/tags/rel_21/bench
113	IDCODE test improved.	mohor	7463d 15h	/dbg_interface/tags/rel_21/bench
112	dbg_tb_defines.v not used.	mohor	7464d 10h	/dbg_interface/tags/rel_21/bench
111	Define tap_defines.v added to test bench.	mohor	7464d 10h	/dbg_interface/tags/rel_21/bench
110	Waiting for "ready" improved.	mohor	7464d 11h	/dbg_interface/tags/rel_21/bench
102	New version.	mohor	7466d 05h	/dbg_interface/tags/rel_21/bench
101	Almost finished.	mohor	7466d 06h	/dbg_interface/tags/rel_21/bench
99	cpu registers added.	mohor	7467d 08h	/dbg_interface/tags/rel_21/bench
96	Working.	mohor	7468d 12h	/dbg_interface/tags/rel_21/bench
95	Temp version.	mohor	7469d 00h	/dbg_interface/tags/rel_21/bench
93	tmp version.	mohor	7470d 12h	/dbg_interface/tags/rel_21/bench

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Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_21/] [bench/] - Rev 158

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