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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog] - Rev 128

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Rev Log message Author Age Path
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7473d 14h /dbg_interface/tags/rel_21/bench/verilog
124 Display for VATS added. mohor 7478d 10h /dbg_interface/tags/rel_21/bench/verilog
121 Port signals are all set to zero after reset. mohor 7481d 11h /dbg_interface/tags/rel_21/bench/verilog
120 test stall_test added. mohor 7481d 14h /dbg_interface/tags/rel_21/bench/verilog
117 Define name changed. mohor 7483d 10h /dbg_interface/tags/rel_21/bench/verilog
116 Data latching changed when testing WB. mohor 7483d 11h /dbg_interface/tags/rel_21/bench/verilog
115 More debug data added. mohor 7483d 14h /dbg_interface/tags/rel_21/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7483d 16h /dbg_interface/tags/rel_21/bench/verilog
113 IDCODE test improved. mohor 7483d 17h /dbg_interface/tags/rel_21/bench/verilog
112 dbg_tb_defines.v not used. mohor 7484d 11h /dbg_interface/tags/rel_21/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7484d 11h /dbg_interface/tags/rel_21/bench/verilog
110 Waiting for "ready" improved. mohor 7484d 12h /dbg_interface/tags/rel_21/bench/verilog
102 New version. mohor 7486d 07h /dbg_interface/tags/rel_21/bench/verilog
101 Almost finished. mohor 7486d 08h /dbg_interface/tags/rel_21/bench/verilog
99 cpu registers added. mohor 7487d 10h /dbg_interface/tags/rel_21/bench/verilog
96 Working. mohor 7488d 14h /dbg_interface/tags/rel_21/bench/verilog
95 Temp version. mohor 7489d 02h /dbg_interface/tags/rel_21/bench/verilog
93 tmp version. mohor 7490d 13h /dbg_interface/tags/rel_21/bench/verilog
92 temp version. mohor 7493d 17h /dbg_interface/tags/rel_21/bench/verilog
91 tmp version. mohor 7494d 12h /dbg_interface/tags/rel_21/bench/verilog

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