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[/] [dbg_interface/] [tags/] [rel_21/] [bench] - Rev 95

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Rev Log message Author Age Path
95 Temp version. mohor 7472d 00h /dbg_interface/tags/rel_21/bench
93 tmp version. mohor 7473d 12h /dbg_interface/tags/rel_21/bench
92 temp version. mohor 7476d 16h /dbg_interface/tags/rel_21/bench
91 tmp version. mohor 7477d 11h /dbg_interface/tags/rel_21/bench
90 tmp version. mohor 7478d 05h /dbg_interface/tags/rel_21/bench
89 temp4 version. mohor 7479d 11h /dbg_interface/tags/rel_21/bench
88 temp3 version. mohor 7480d 06h /dbg_interface/tags/rel_21/bench
87 tmp2 version. mohor 7481d 11h /dbg_interface/tags/rel_21/bench
80 New version of the debug interface. Not finished, yet. mohor 7494d 09h /dbg_interface/tags/rel_21/bench
75 Simulation files. mohor 7555d 07h /dbg_interface/tags/rel_21/bench
73 CRC logic changed. mohor 7555d 07h /dbg_interface/tags/rel_21/bench
63 Three more chains added for cpu debug access. simons 7611d 09h /dbg_interface/tags/rel_21/bench
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 09h /dbg_interface/tags/rel_21/bench
38 Few outputs for boundary scan chain added. mohor 8145d 09h /dbg_interface/tags/rel_21/bench
36 Structure changed. Hooks for jtag chain added. mohor 8149d 08h /dbg_interface/tags/rel_21/bench
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8289d 12h /dbg_interface/tags/rel_21/bench
15 bs_chain_o added. mohor 8291d 13h /dbg_interface/tags/rel_21/bench
13 Signal names changed to lowercase. mohor 8292d 13h /dbg_interface/tags/rel_21/bench
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8293d 13h /dbg_interface/tags/rel_21/bench
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8314d 09h /dbg_interface/tags/rel_21/bench

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