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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] [verilog/] [dbg_top.v] - Rev 101

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Rev Log message Author Age Path
101 Almost finished. mohor 7506d 18h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
99 cpu registers added. mohor 7507d 20h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
95 Temp version. mohor 7509d 12h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7531d 20h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
73 CRC logic changed. mohor 7592d 19h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
67 Lower two address lines must be always zero. simons 7627d 21h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
65 WB_CNTL register added, some syncronization fixes. simons 7628d 21h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
63 Three more chains added for cpu debug access. simons 7648d 21h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
57 Multiple cpu support added. simons 7676d 23h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7943d 21h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7971d 08h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8126d 20h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
44 Signal names changed to lower case. mohor 8141d 22h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
43 Intentional error removed. mohor 8146d 22h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
42 A block for checking possible simulation/synthesis missmatch added. mohor 8147d 00h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8183d 01h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
36 Structure changed. Hooks for jtag chain added. mohor 8186d 20h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8216d 23h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
32 Stupid bug that was entered by previous update fixed. mohor 8217d 22h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
31 trst synchronization is not needed and was removed. mohor 8217d 23h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v

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