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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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158 root 5663d 21h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
134 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7486d 00h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7530d 07h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
123 All flipflops are reset. mohor 7535d 03h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
117 Define name changed. mohor 7540d 03h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7541d 10h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
106 Sensitivity list updated. simons 7542d 08h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
101 Almost finished. mohor 7543d 00h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
99 cpu registers added. mohor 7544d 02h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
95 Temp version. mohor 7545d 18h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7568d 02h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
73 CRC logic changed. mohor 7629d 01h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
67 Lower two address lines must be always zero. simons 7664d 03h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
65 WB_CNTL register added, some syncronization fixes. simons 7665d 02h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
63 Three more chains added for cpu debug access. simons 7685d 03h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
57 Multiple cpu support added. simons 7713d 05h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7980d 03h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 8007d 14h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8163d 02h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
44 Signal names changed to lower case. mohor 8178d 04h /dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v

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