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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] [verilog/] [dbg_top.v] - Rev 57

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Rev	Log message	Author	Age	Path
57	Multiple cpu support added.	simons	7676d 23h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7943d 21h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7971d 09h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8126d 21h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
44	Signal names changed to lower case.	mohor	8141d 22h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
43	Intentional error removed.	mohor	8146d 22h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8147d 00h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8183d 01h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
36	Structure changed. Hooks for jtag chain added.	mohor	8186d 20h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8216d 23h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
32	Stupid bug that was entered by previous update fixed.	mohor	8217d 22h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
31	trst synchronization is not needed and was removed.	mohor	8217d 23h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8229d 03h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
28	TDO and TDO Enable signal are separated into two signals.	mohor	8265d 00h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
25	trst signal is synchronized to wb_clk_i.	mohor	8279d 22h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
22	Register length fixed.	mohor	8287d 02h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
21	CRC is returned when chain selection data is transmitted.	mohor	8287d 22h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8289d 01h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8301d 01h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v
18	Reset signals are not combined any more.	mohor	8303d 10h	/dbg_interface/tags/rel_21/rtl/verilog/dbg_top.v

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[/] [dbg_interface/] [tags/] [rel_21/] [rtl/] [verilog/] [dbg_top.v] - Rev 57

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