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[/] [dbg_interface/] [tags/] [rel_22] - Rev 89

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Rev Log message Author Age Path
89 temp4 version. mohor 7524d 08h /dbg_interface/tags/rel_22
88 temp3 version. mohor 7525d 03h /dbg_interface/tags/rel_22
87 tmp2 version. mohor 7526d 08h /dbg_interface/tags/rel_22
86 Tmp version. mohor 7539d 04h /dbg_interface/tags/rel_22
85 New directory structure. New debug interface. mohor 7539d 05h /dbg_interface/tags/rel_22
84 Removed files that are not needed any more. mohor 7539d 05h /dbg_interface/tags/rel_22
83 Small fix. mohor 7539d 05h /dbg_interface/tags/rel_22
82 New directory structure. New version of the debug interface. mohor 7539d 05h /dbg_interface/tags/rel_22
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7539d 05h /dbg_interface/tags/rel_22
80 New version of the debug interface. Not finished, yet. mohor 7539d 06h /dbg_interface/tags/rel_22
77 MBIST chain connection fixed. mohor 7600d 02h /dbg_interface/tags/rel_22
75 Simulation files. mohor 7600d 04h /dbg_interface/tags/rel_22
74 Removed. mohor 7600d 04h /dbg_interface/tags/rel_22
73 CRC logic changed. mohor 7600d 04h /dbg_interface/tags/rel_22
71 Mbist support added. simons 7602d 10h /dbg_interface/tags/rel_22
70 A pdf copy of existing doc document. simons 7609d 12h /dbg_interface/tags/rel_22
69 WBCNTL added, multiple CPU support described. simons 7630d 02h /dbg_interface/tags/rel_22
67 Lower two address lines must be always zero. simons 7635d 06h /dbg_interface/tags/rel_22
65 WB_CNTL register added, some syncronization fixes. simons 7636d 06h /dbg_interface/tags/rel_22
63 Three more chains added for cpu debug access. simons 7656d 06h /dbg_interface/tags/rel_22

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