URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] [dbg_crc8_d1.v] - Rev 26

Rev	Log message	Author	Age	Path
26	Warnings from synthesys tools fixed.	mohor	8288d 22h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_crc8_d1.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8298d 21h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_crc8_d1.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8336d 20h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_crc8_d1.v
9	Working version. Few bugs fixed, comments added.	mohor	8365d 22h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_crc8_d1.v
2	Initial official release.	mohor	8372d 18h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_crc8_d1.v