URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] [verilog/] [dbg_register.v] - Rev 46

Rev	Log message	Author	Age	Path
46	Asynchronous reset used instead of synchronous.	mohor	8145d 00h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
44	Signal names changed to lower case.	mohor	8151d 19h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8298d 22h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8336d 21h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v
2	Initial official release.	mohor	8372d 18h	/dbg_interface/tags/rel_6/rtl/verilog/dbg_register.v