URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl] - Rev 22

Rev	Log message	Author	Age	Path
22	Register length fixed.	mohor	8266d 02h	/dbg_interface/tags/rel_6/rtl
21	CRC is returned when chain selection data is transmitted.	mohor	8266d 22h	/dbg_interface/tags/rel_6/rtl
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8268d 01h	/dbg_interface/tags/rel_6/rtl
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8280d 02h	/dbg_interface/tags/rel_6/rtl
18	Reset signals are not combined any more.	mohor	8282d 11h	/dbg_interface/tags/rel_6/rtl
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8306d 00h	/dbg_interface/tags/rel_6/rtl
15	bs_chain_o added.	mohor	8308d 01h	/dbg_interface/tags/rel_6/rtl
13	Signal names changed to lowercase.	mohor	8309d 02h	/dbg_interface/tags/rel_6/rtl
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8310d 02h	/dbg_interface/tags/rel_6/rtl
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8330d 22h	/dbg_interface/tags/rel_6/rtl
9	Working version. Few bugs fixed, comments added.	mohor	8335d 02h	/dbg_interface/tags/rel_6/rtl
8	Asynchronous set/reset not used in trace any more.	mohor	8336d 00h	/dbg_interface/tags/rel_6/rtl
5	Trace fixed. Some registers changed, trace simplified.	mohor	8336d 22h	/dbg_interface/tags/rel_6/rtl
2	Initial official release.	mohor	8341d 22h	/dbg_interface/tags/rel_6/rtl