URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_crc8_d1.v] - Rev 17

Rev	Log message	Author	Age	Path
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8288d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
9	Working version. Few bugs fixed, comments added.	mohor	8317d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v
2	Initial official release.	mohor	8324d 03h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_crc8_d1.v