URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_defines.v] - Rev 30

Rev	Log message	Author	Age	Path
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8190d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
27	Warnings from synthesys tools fixed.	mohor	8240d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
23	Trace disabled by default.	mohor	8248d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8292d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8313d 01h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
9	Working version. Few bugs fixed, comments added.	mohor	8317d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8319d 00h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v
2	Initial official release.	mohor	8324d 01h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_defines.v