URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_registers.v] - Rev 44

Rev	Log message	Author	Age	Path
44	Signal names changed to lower case.	mohor	8103d 04h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_registers.v
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8250d 06h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_registers.v
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8288d 05h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_registers.v
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8292d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_registers.v
5	Trace fixed. Some registers changed, trace simplified.	mohor	8319d 03h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_registers.v
2	Initial official release.	mohor	8324d 03h	/dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_registers.v