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[/] [dbg_interface/] [trunk/] [bench/] [verilog] - Rev 135

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Rev Log message Author Age Path
135 'hz changed to 1'hz because Icarus complains. igorm 7444d 14h /dbg_interface/trunk/bench/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7489d 19h /dbg_interface/trunk/bench/verilog
124 Display for VATS added. mohor 7494d 16h /dbg_interface/trunk/bench/verilog
121 Port signals are all set to zero after reset. mohor 7497d 16h /dbg_interface/trunk/bench/verilog
120 test stall_test added. mohor 7497d 19h /dbg_interface/trunk/bench/verilog
117 Define name changed. mohor 7499d 15h /dbg_interface/trunk/bench/verilog
116 Data latching changed when testing WB. mohor 7499d 16h /dbg_interface/trunk/bench/verilog
115 More debug data added. mohor 7499d 19h /dbg_interface/trunk/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7499d 21h /dbg_interface/trunk/bench/verilog
113 IDCODE test improved. mohor 7499d 22h /dbg_interface/trunk/bench/verilog
112 dbg_tb_defines.v not used. mohor 7500d 16h /dbg_interface/trunk/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7500d 17h /dbg_interface/trunk/bench/verilog
110 Waiting for "ready" improved. mohor 7500d 17h /dbg_interface/trunk/bench/verilog
102 New version. mohor 7502d 12h /dbg_interface/trunk/bench/verilog
101 Almost finished. mohor 7502d 13h /dbg_interface/trunk/bench/verilog
99 cpu registers added. mohor 7503d 15h /dbg_interface/trunk/bench/verilog
96 Working. mohor 7504d 19h /dbg_interface/trunk/bench/verilog
95 Temp version. mohor 7505d 07h /dbg_interface/trunk/bench/verilog
93 tmp version. mohor 7506d 18h /dbg_interface/trunk/bench/verilog
92 temp version. mohor 7509d 22h /dbg_interface/trunk/bench/verilog

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