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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Rev 144

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Rev	Log message	Author	Age	Path
144	Port names and defines for the supported CPUs changed.	igorm	7406d 17h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
139	New release of the debug interface (3rd. release).	igorm	7410d 09h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
138	Temp version before changing dbg interface.	igorm	7416d 12h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
128	Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are turned on.	mohor	7468d 19h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
123	All flipflops are reset.	mohor	7473d 15h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
117	Define name changed.	mohor	7478d 15h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7479d 22h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
106	Sensitivity list updated.	simons	7480d 20h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
101	Almost finished.	mohor	7481d 12h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
99	cpu registers added.	mohor	7482d 14h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
95	Temp version.	mohor	7484d 06h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7506d 14h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
73	CRC logic changed.	mohor	7567d 13h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
67	Lower two address lines must be always zero.	simons	7602d 15h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
65	WB_CNTL register added, some syncronization fixes.	simons	7603d 14h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
63	Three more chains added for cpu debug access.	simons	7623d 15h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
57	Multiple cpu support added.	simons	7651d 17h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7918d 15h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7946d 02h	/dbg_interface/trunk/rtl/verilog/dbg_top.v
47	mon_cntl_o signals that controls monitor mux added.	mohor	8101d 14h	/dbg_interface/trunk/rtl/verilog/dbg_top.v

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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Rev 144

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