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[/] [dbg_interface/] [trunk] - Rev 75

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Rev Log message Author Age Path
75 Simulation files. mohor 7589d 10h /dbg_interface/trunk
74 Removed. mohor 7589d 10h /dbg_interface/trunk
73 CRC logic changed. mohor 7589d 10h /dbg_interface/trunk
71 Mbist support added. simons 7591d 17h /dbg_interface/trunk
70 A pdf copy of existing doc document. simons 7598d 19h /dbg_interface/trunk
69 WBCNTL added, multiple CPU support described. simons 7619d 08h /dbg_interface/trunk
67 Lower two address lines must be always zero. simons 7624d 13h /dbg_interface/trunk
65 WB_CNTL register added, some syncronization fixes. simons 7625d 12h /dbg_interface/trunk
63 Three more chains added for cpu debug access. simons 7645d 13h /dbg_interface/trunk
61 Lapsus fixed. simons 7673d 13h /dbg_interface/trunk
59 Reset value for riscsel register set to 1. simons 7673d 13h /dbg_interface/trunk
57 Multiple cpu support added. simons 7673d 14h /dbg_interface/trunk
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7940d 11h /dbg_interface/trunk
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7940d 11h /dbg_interface/trunk
53 Trst active high. Inverted on higher layer. mohor 7940d 12h /dbg_interface/trunk
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7940d 12h /dbg_interface/trunk
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7968d 00h /dbg_interface/trunk
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7968d 01h /dbg_interface/trunk
47 mon_cntl_o signals that controls monitor mux added. mohor 8123d 12h /dbg_interface/trunk
46 Asynchronous reset used instead of synchronous. mohor 8131d 18h /dbg_interface/trunk

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