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[/] [dblclockfft/] [trunk/] [bench/] [cpp/] [butterfly_tb.cpp] - Rev 13

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Rev	Log message	Author	Age	Path
13	I updated the butterfly testbench to automatically determine the delay internal to the chip and multiply, and then to use that delay in determining whether the values were accurate or not. This is better than the fixed delay approach that was used before. The change was necessitated by an attempt to use a different multiply structure that had a different internal delay to it. (The multiply didn't work out, as it only worked on operands with identical numbers of bits.)	dgisselq	3420d 08h	/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp
8	This completes the initial work on a test bench for the FFT stage. I chose to test the odd 2048 stage only, but (hopefully) the testbench will still apply to all other stages as well. At any rate, based upon some trial runs, it looks like the FFT may be starting to work as well. More testing is needed, for certain, but to do that I'm going to have to figure out just what tests are needed, and how exactly to apply those tests within the test bench construct.	dgisselq	3426d 15h	/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp
6	Lots of work accomplished today. Test benches now exist and work for the: butterfly, multiply, bitreversal, pairwise FFT stage (dblstage), and the four-wise FFT stage (qtrstage). Work continues on the single (generic) FFT stage, and (of course) the FFT isn't ready yet. A second commit will follow this one shortly with the new files added (oops!--I should've added them this time--my bad.)	dgisselq	3427d 02h	/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp
5	The butterfly_tb is now written, and the butterfly succeeds at the test bench!	dgisselq	3427d 09h	/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp
4	Bench tests updated, they now state SUCCESS upon successful completion, return a 0 on success, and all bench tests test all function outputs (now).	dgisselq	3427d 14h	/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp
3	The first upload of the s/w didn't take. Had it taken, the comment would've been: This is the first upload of the double clocked FFT software. While it should (roughly) be complete, a lot of work remains to be done--primarily in building test benches, modifying the interface of fftgen to make it more friendly, etc. In fact, the c++ code not only compiles, but the Verilog code it produces actually builds as well! Now, however, I have several test benches written, and have verified the unit functionality of the multiply, bit reversal stage, the dblstage (FFT len 2), and the qtrstage (FFT len 4). I then took a closer look at the multiply, discovered it failed at signed integers and rebuilt it. The new test bench tests the full 16-bit signed integer support properly. This leaves butterflies and generic FFT stages that still need test benches, as does the main (I)FFT program.	dgisselq	3427d 15h	/dblclockfft/trunk/bench/cpp/butterfly_tb.cpp

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